
// data memory
module dmem(clk, DMWr, addr, din, dout,pc);
   input          clk;
   input          DMWr;
   input  [31:0]   addr;
   input  [31:0]  din;
   output [31:0]  dout;
   input [31:0]     pc;//
     
   reg [31:0] dmem[127:0];
   
   always @(posedge clk)
      if (DMWr) begin
         dmem[addr[8:2]] <= din;
        //  //$display("dmem[0x%8X] = 0x%8X,", addr << 2, din); 
  
      $display("pc = %8X: dataaddr = %8X, memdata = %8X",pc,addr,din); 
      end
   
   assign dout = dmem[addr[8:2]];
    
endmodule    
